MA1916

7/11

TIMING DIAGRAMS

Note: Bytes of MSG labelled 0 to 222 x I

Bytes of RSE_OUT labelled 0 to 254 x I

Bits labelled 0 to 7

I = Interleave depth of 1, 4 or 5

Figure 6: RS Encoder Timings

*

Notes: 1. If CE_CLK is driven by CLKS, the user can capture CE_OUT on the falling edge of CLK_OUT.

2. Arrows show which O/P bits correspond to which I/P bit.

See Note 2

Figure 7: Convolution Encoder Timings