MA9264

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SIGNAL DEFINITIONS

A0-12

Address input pins which select a particular eight bit word within

the memory array.

D0-7

Bidirectional data pins which serve as data outputs during a read

operation and as data inputs during a write operation.

CS

Chip Select, which, at low level, activates a read or write

operation. When at a high level it defaults the SRAM to a

prechargencondition and holds the data output drivers in a high

impedance state.

WE

Write Enable which when at a low level enables a write and holds

data output drivers in a high impedance state. When at a high

level, it enables a read.

OE

Output Enable which when at a high level holds the data output

drivers in a high impedance state. When at a low level, data

output driver state is defined by

CS, WE and CE. If this signal is

not used it must be connected to VSS.

CE

Chip Enable which when at a high level allows normal operation.

When at a low level it defaults the SRAM to a precharge

condition, disables the input circuits on all input pins and holds

the data output drivers in a high impedance state. If this signal

is not used it must be connected to VDD.