MAS281 datasheet(41/55 Pages) DYNEX

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MAS281

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8.0 TIMING PARAMETERS

NO.

Parameter

Test Condition

Min.

Max.

Units

(notes 1 & 9)

(note 2)

RESET setup to SYNC lo (note 3)

RESET hold after SYNC lo (note 3)

RESET hi to RESET lo (note 3)

SYNC

OSC hi to SYNC lo

Load 1

OSC hi to SYNC hi

Load 1

SYNC lo to SYNC lo (notes 4 & 5)

Load 1

5T - 2

5T + 2

SYNC lo to AS hi (note 6)

Load 1

1T - 10

1T + 5

SYNC lo to AS lo

Load 1

2.5T - 10

2.5T + 15

SYNC lo to DS lo (read)

Load 1

3T - 5

3T + 20

SYNC lo to DS hi (read)

Load 1

SYNC lo to DS lo (write)

Load 1

3T - 5

3T + 22

SYNC lo to DS hi (write) (note 5)

Load 1

4.5T -5

4.5T + 10

SYNC lo to DD lo

Load 1

3 T + 20

3T + 60

SYNC lo to DD hi

Load 1

SYNC lo to Address valid

Load 2

Address valid after SYNC lo

Load 2

3T + 15

SYNC lo to AD Bus Hi-Z (read)

(notes 7 & 10)

Load 2

3T + 50

SYNC lo to AD Bus active(read) (note 10) Load 2

SYNC lo to Data valid (write)

Load 2

3T + 45

Data valid after SYNC lo (write)

Load 2

Data set up to SYNC lo (read)

Data hold after SYNC lo (read) (note 8)

Load 2

SYNC lo to M/IO, RD/VV, IN/OP valid

Load 1

M/IO, RD/WN, IN/OP valid after SYNC lo Load 1

RDY setup to OSC lo

RDY hold after OSC lo

SYNC lo to DMAE valid

Load 1

DMAE valid after SYNC lo

Load 1

DMAR setup to SYNC lo

DMAR hold after SYNC lo

NOTES:

Mil-Std-883, method 5005, subgroups 9, 10, 11

1. Unless otherwise noted, test condltions are as follows: OSC duty cycle = 50%, input rise and fall time < 5ns, timing

measured from 50% of VDD points.

2. t = 1 OSC period. 0.5t implies a 50% OSC duty cycle; fractional t’s may be adjusted to reflect actual OSC duty cycle.

3. Data obtained by characterisation or analysis, is not routinely measured.

4. Add 1t for potential branch cycle.

5. Add 1t for internal XIO cycle; nt for n memory wait states.

6. Excluding DMA or HOLD conditions.

7. Measured to pre-Hi-Z steady state

± 10% of VDD.

8. Measurement minus 1x10-7 in [1-(VlL-0 5/VDD-0.5)] nsecs.

9. Output references SYNC, DMAK, and HLDAK drive into load 1.

10. Guaranteed by component LSI testing: not measured on microprocessor module.

Table 10. Timing Parameters

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