REV. B

–6–

ADG528A/ADG529A

TRUTH TABLES

A2 A1 A0 EN

WR RS ON SWITCH PAIR

XXXX

1Retains Previous Switch Condition

XXXX

X

0

NONE (Address and Enable

Latches Cleared)

XXX0

0

1

NONE

0001

0

1

1

0011

0

1

2

0101

0

1

3

0111

0

1

4

1001

0

1

5

1011

0

1

6

1101

0

1

7

1111

0

1

8

X = Don’t Care

ADG528A

A1 A0 EN

WR RS ON SWITCH PAIR

XXX

1Retains Previous Switch Condition

XXX

X0

NONE (Address and Enable Latches

Cleared)

XX0

01

NONE

001

0

1

1

011

0

1

2

101

0

1

3

111

0

1

4

X = Don’t Care

ADG529A

TIMING DIAGRAMS

Figure 1.

Figure 2.

Figure 1 shows the timing sequence for latching the switch

address and enable inputs. The latches are level sensitive; there-

fore, while

WR is held low, the latches are transparent and the

switches respond to the address and enable inputs. This input

data is latched on the rising edge of

WR.

Note: All digital input signals rise and fall times measured from