IRS2332SPBF datasheet(21/39 Pages) IRF

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IRS233(0,2)(D)(S&J)PbF

Figure 25: Parasitic Elements

Figure 26: VS positive

Figure 27: VS negative

In a typical motor drive system, dV/dt is typically designed to be in the range of 3-5 V/ns. The negative VS transient voltage

can exceed this range during some events such as short circuit and over-current shutdown, when di/dt is greater than in

normal operation.

International Rectifier’s HVICs have been designed for the robustness required in many of today’s demanding applications. An

indication of the IRS233(0,2)(D)’s robustness can be seen in Figure 28, where there is represented the IRS233(0,2)(D) Safe

Operating Area at VBS=15V based on repetitive negative VS spikes. A negative VS transient voltage falling in the grey area

(outside SOA) may lead to IC permanent damage; viceversa unwanted functional anomalies or permanent damage to the IC

do not appear if negative Vs transients fall inside SOA.

At VBS=15V in case of -VS transients greater than -16.5 V for a period of time greater than 50 ns; the HVIC will hold by design

the high-side outputs in the off state for 4.5 µs.

Figure 28: Negative VS transient SOA for IRS233(0,2)(D)

Even though the IRS233(0,2)(D) has been shown able to handle these large negative VS transient conditions, it is highly

recommended that the circuit designer always limit the negative VS transients as much as possible by careful PCB layout and

component use.

IRS2332SPBF 데이터시트(PDF) 21 Page - International Rectifier