Bluegiga Technologies Oy

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free for other uses. When configured as SPI slaves, the USARTs sample the input signal using SCK directly

instead of using some oversampling scheme, and are thus well-suited for high data rates.

The AES encryption/decryption core allows the user to encrypt and decrypt data using the AES algorithm with

128-bit keys. The AES core also supports ECB, CBC, CFB, OFB, CTR, and CBC-MAC, as well as hardware

support for CCM.

The ADC supports 7 to 12 bits of resolution with a corresponding range of bandwidths from 30-kHz to 4-kHz,

respectively. DC and audio conversions with up to eight input channels (I/O controller pins) are possible. The

inputs can be selected as single-ended or differential. The reference voltage can be internal, AVDD, or a

single-ended or differential external signal. The ADC also has a temperature-sensor input channel. The ADC

can automate the process of periodic sampling or conversion over a sequence of channels.

The I

operation. I

(up to 100 kbps) and fast mode (up to 400 kbps). In addition, 7-bit device addressing modes are supported, as

well as master and slave modes..

The ultralow-power analog comparator enables applications to wake up from PM2 or PM3 based on an analog

signal. Both inputs are brought out to pins; the reference voltage must be provided externally. The comparator

output is connected to the I/O controller interrupt detector and can be treated by the MCU as a regular I/O pin

interrupt.

RF front end

RF front end includes combined matched balun and low pass filter, and ceramic chip antenna with matching

network. Optimal matching combined with effective low pass filter provides extremely low in-band spurious

emissions and harmonics.