A3P030 datasheet(69/210 Pages) MICROSEMI

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ProASIC3 Flash Family FPGAs

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Timing Characteristics

Differential I/O Characteristics

Physical Implementation

Configuration of the I/O modules as a differential pair is handled by Microsemi Designer software when

the user instantiates a differential I/O macro in the design.

Differential I/Os can also be used in conjunction with the embedded Input Register (InReg), Output

support for bidirectional I/Os or tristates with the LVPECL standards.

LVDS

Low-Voltage Differential Signaling (ANSI/TIA/EIA-644) is a high-speed, differential I/O standard. It

requires that one data bit be carried through two signal lines, so two pins are needed. It also requires

external resistor termination.

The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-11. The

building blocks of the LVDS transmitter-receiver are one transmitter macro, one receiver macro, three

board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver

resistors are different from those used in the LVPECL implementation because the output standard

specifications are different.

Along with LVDS I/O, ProASIC3 also supports Bus LVDS structure and Multipoint LVDS (M-LVDS)

configuration (up to 40 nodes).

Table 2-88 • 3.3 V PCI/PCI-X

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Advanced I/O Banks

Speed Grade

tDOUT

tDP

tDIN

tPY

tEOUT

tZL

tZH

tLZ

tHZ

tZLS

tZHS

Units

Std.

0.66

2.68

0.04

0.86

0.43

2.73

1.95

3.21

3.58

4.97

4.19

–1

0.56

2.28

0.04

0.73

0.36

2.32

1.66

2.73

3.05

4.22

3.56

–2

0.49

2.00

0.03

0.65

0.32

2.04

1.46

2.40

2.68

3.71

3.13

Note:

For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

Table 2-89 • 3.3 V PCI/PCI-X

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Applicable to Standard Plus I/O Banks

Speed Grade

tDOUT

tDP

tDIN

tPY

tEOUT

tZL

tZH

tLZ

tHZ

tZLS

tZHS

Units

Std.

0.66

2.31

0.04

0.85

0.43

2.35

1.70

2.79

3.22

4.59

3.94

–1

0.56

1.96

0.04

0.72

0.36

2.00

1.45

2.37

2.74

3.90

3.35

–2

0.49

1.72

0.03

0.64

0.32

1.76

1.27

2.08

2.41

3.42

2.94

Note:

For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

Figure 2-11 • LVDS Circuit Diagram and Board-Level Implementation

140



100



Z0 = 50 

165



165



–

INBUF_LVDS

OUTBUF_LVDS

FPGA

Bourns Part Number: CAT16-LV4F12

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