Bottom View

Top View

Top Marking

X

B1

A1

B2

A2

GND

B1

A1

B2

A2

GND

1.0 µF

GND

GND

1.0 µF

LP5990

Capacitor Case

Size = 0402

LP5990

SNVS438B – APRIL 2007 – REVISED DECEMBER 2007

www.ti.com

Typical Application Circuit

Connection Diagrams

Figure 1. 4-Bump Thin micro SMD Package, 0.4mm pitch

NS Package Number TMD04

The actual physical placement of the package marking will vary from part to part.

Pin Functions

Pin Descriptions

Pin No.

Symbol

Name and Function

micro SMD

A2

Enable input; disables the regulator when

≤ 0.35V. Enables the regulator when ≥ 1.0V.

A1

GND

Common ground.

B1

Output voltage. A 1.0

μF Low ESR capacitor should be connected to this Pin. Connect

this output to the load circuit.

B2

Input voltage supply. A 1.0 µF capacitor should be connected at this input.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

2

Submit Documentation Feedback

Copyright © 2007, Texas Instruments Incorporated

Product Folder Links: LP5990