전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

Preview PDF HTML

PM8803TR 데이터시트(PDF) 15 Page - STMicroelectronics

부품명 PM8803TR
상세설명  High-efficiency, IEEE 802.3at compliant integrated PoE-PD interface and PWM controller
PDF  34 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

PM8803TR 데이터시트(HTML) 15 Page - STMicroelectronics

Back Button PM8803TR Datasheet HTML 11Page - STMicroelectronics PM8803TR Datasheet HTML 12Page - STMicroelectronics PM8803TR Datasheet HTML 13Page - STMicroelectronics PM8803TR Datasheet HTML 14Page - STMicroelectronics PM8803TR Datasheet HTML 15Page - STMicroelectronics PM8803TR Datasheet HTML 16Page - STMicroelectronics PM8803TR Datasheet HTML 17Page - STMicroelectronics PM8803TR Datasheet HTML 18Page - STMicroelectronics PM8803TR Datasheet HTML 19Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 15 / 34 page
background image
PM8803
Electrical specifications
Doc ID 018559 Rev 2
15/34
Table 6.
Electrical characteristics - SMPS section
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Oscillator
Fosc
Frequency accuracy
In the range 100 to 500 kHz
+/-10
%
Frequency
programmability
RFRS = 100 kΩ
220
245
270
kHz
RFRS = 47.5 kΩ
445
495
545
kHz
Frequency range
100
1000
kHz
FRS voltage
1.20
1.25
1.30
V
Delay time
GAT1 to GAT2 delay time
RDT = 20 k
Ω, GAT1and GAT2 open
32
ns
RDT = 200 k
Ω, GAT1and GAT2 open
320
ns
DT voltage
1.20
1.25
1.30
V
Soft-start
TSS
Soft-start time
Over CTL full range (0 to 3 V), at
Fosc = 250 kHz
12.3
ms
Current limit
Delay to output
Guaranteed by design
20
ns
Cycle-by-cycle current
limit threshold voltage
0.44
0.50
0.56
V
Leading edge blanking
time
45
60
75
ns
Slope compensation
current
Sourced by CS pin
45
μA
PWM comparator
Delay to output
Guaranteed by design
25
ns
Minimum duty cycle
CTL = 0, CS = 0
0
%
Maximum duty cycle
CTL = 2 V, CS = 0, Fosc = 250 kHz
75
80
85
%
CTL to PWM gain
Guaranteed by design
1 : 4
CTL operative range
1
3
V
Output driver GAT1
Output high
IGD = 100 mA
VC-
0.25
VC-0.5
V
Output low
IGD = -100 mA
0.25
0.5
V
Fall time
CLOAD = 3.3 nF, VC = 10 V
Guaranteed by design
40
ns
Rise time
CLOAD = 3.3 nF, VC = 10 V
Guaranteed by design
45
ns



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com