MB40C318VPFV datasheet(9/16 Pages) FUJITSU

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MB40C318V

s TIMING DIAGRAM 1

Differential CLK input-straight output mode

• CLKEP = CLKEN = 140 MHz (max)

• CLKA = CLKB = “L” (DVSS)

• CKSEL = “H” (AVDD)

•DSEL = “H” (DVDD)

• RESET = “H” (DVDDI)

•CE = “L” (AVSS)

•OE = “L” (DVSS)

• Differential CLK input — Solid line: CLKEP, Dotted line: CLKEN

•VINA input — Sampling at CLKEP rising

(CLKEN falling)

•DA0 to DA7 — Output (after 5 CLK + tpdS from Sampling) at CLKEP rising

(CLKEN falling)

VIHD

VILD

VOHD

VOLD

DA0 to DA7

VOHD

VOLD

DB0 to DB7

VOHD

VOLD

CLKOA

VOHD

VOLD

CLKOB

DVDDI

− 1.1 V

DVDDI

− 1.45 V

0.4 V

+ 1

DVDD

− 0.4 V

0.4 V

tAD

tWS+

tWS−

− 3N − 2N − 1

− 4

− 5

− 6

− 7

− 1N + 1N + 2N + 3N + 4N + 5N + 6N + 7

tpdSO (typ)

tpdSO (min)

tpdSO (max)

DVDD

− 0.4 V

tpdS (typ)

tpdS (min)

tpdS(max)

Differential

CLK input

VINA input

ALL “L” fix

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