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MB40C338VPFV 데이터시트(PDF) 13 Page - fujitsu semiconductor |
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MB40C338VPFV 데이터시트(HTML) 13 Page - fujitsu semiconductor |
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13 / 19 page ![]() MB40C338V 13 • Demultiplex Output (in- phase) Mode (Timing Diagram 2) • ADIN input - Sampling at CLK rising (at CLKB falling) •DA0 to DA7 - Output (after 6 CLK + tpd (CLK-DATA2) from sampling ) at CLK rising (at CLKB falling) •DB0 to DB7 - Output (after 5 CLK + tpd (CLK-DATA2) from sampling ) at CLK rising (at CLKB falling) tpd (HSYNC-CLK) tpd (CLK-DSYNC) tAD tpd (CLK-ADCLK2) tpd (CLK-DATA2) N X X X X X X X X X X X X X X X N N + 1 N N + 2 N + 3 N + 2 N + 1N + 2N + 3N + 4N + 5N + 6N + 7N + 8N + 9 HSYNC input CLKB output CLK output DSYNC output ADCLKA output ADCLKB output ADIN input DA0 to DA7 output DB0 to DB7 output OF output VOLD VOLD VOLD VOLD VOLD VOLD VOLD VOHD VOHD VOHD VOHD VOHD VOHD VOHD VIHD VILD |
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