MB40C348V

4

(Continued)

Note: The values in parentheses are standard.

Pin No.

Symbol

Description

99

EXPCLKB

Differential clock (negative-phase) input pin for A/D converter

Fix to “H” level when unused.

PECL level

100

EXPCLK

Differential clock (positive-phase) input pin for A/D converter

Fix to “L” level when unused.

8

PCLP

Clamp pulse input pin

113

Internal current setting pin (Add 12 k

Ω for AVss)

103

DSYNC

Delay sync signal output pin

102

DSYNCB

Inverted delay sync signal output pin

95

CLK

Clock output pin (See “ s TIMING DIAGRAM ”.)

94

CLKB

97

ADCLKA

96

ADCLKB

83 to 90

61 to 68

39 to 46

Digital output pin (Port A)

71 to 78

51 to 58

29 to 36

Digital output pin (Port B)

101

COUT

PLL counter output pin

115

LPF

External capacitor / resistor connection pin

117

HHOLD

Phase detector operation is hold by input “H” level

118

HSYNC

Horizontal sync signal input pin

Internal voltage output pin (Add 3.3 µF for AVss)

104

OF

Overflow output pin (“H” level output at overflow)