TEF6894H datasheet(8/55 Pages) PHILIPS

8 / 55 page

2003 Oct 21

Philips Semiconductors

Product speciﬁcation

Car radio integrated signal processor

TEF6894H

DGND

digital ground

SDA

I2C-bus data input or output

SCL

I2C-bus clock input

ADDR

address select input

SYMBOL

DESCRIPTION

handbook, full pagewidth

TEF6894H

MHC421

LEVEL

GND

SCLG

SDAG

FMMPX

MPXRDS

i.c.

AFHOLD

AFSAMP

FREF

i.c.

NAV

i.c.

RROUT

LROUT

RFOUT

LFOUT

PHCM

PHONE

TAPEL

TAPER

Fig.2 Pin configuration.

FUNCTIONAL DESCRIPTION

7.1

Stereo decoder

The FMMPX input is the input for the MPX signal from the

tuner. The input gain can be selected in three settings to

match the input to the RF front-end circuit. A fourth setting

is used for weather band mode, which may require a gain

of 23.5 dB.

A low-pass filter provides the necessary signal delay for

FM noise blanking and suppression of high frequency

interferences into the stereo decoder input. The output

signal of this filter is fed to the roll-off correction circuit. This

circuit compensates the frequency response caused by

the low-pass characteristic of the tuner circuit with its

IF filters. The roll-off correction circuit is adjustable in four

settings to compensate different frequency responses of

the tuner part.

The MPX signal is decoded in the stereo decoder part.

A PLL is used for the regeneration of the 38 kHz

subcarrier. The fully integrated oscillator is adjusted by a

digital auxiliary PLL into the capture range of the main PLL.

The auxiliary PLL needs an external reference frequency

(75.4 kHz) which is provided by the tuner ICs of the NICE

family (TEA684x). The required 19 and 38 kHz signals are

generated by division of the oscillator output signal in a

logic circuit. The 19 kHz quadrature phase signal is fed to

the 19 kHz phase detector, where it is compared with the

incoming pilot tone. The DC output signal of the phase

detector controls the oscillator (PLL).

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