COP8AME9 datasheet(21/102 Pages) TI1

21 / 102 page

COP8AME9, COP8ANE9

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SNOS930F – MARCH 2001 – REVISED MARCH 2013

Case 2 shows a subsequent dip in the supply voltage which goes below the approximate 1.8V level. As VCC

drops below Vbor, the internal RESET signal is asserted. When VCC rises back above the 1.8V level, td is started.

Since the power supply rise time is longer for this case, td has expired before VCC rises above Vbor and tid starts

immediately when VCC is greater than Vbor.

Case 3 shows a dip in the supply where VCC drops below Vbor, but not below 1.8V. On-chip RESET is asserted

when VCC goes below Vbor and tid starts as soon as the supply goes back above Vbor.

The internal reset will not be turned off until the Idle Timer underflows. The internal reset will perform the same

functions as external reset. The device is ensured to operate at the specified frequency down to the specified

brownout voltage. After the underflow, the logic is designed such that no additional internal resets occur as long

as VCC remains above the brownout voltage.

The device is relatively immune to short duration negative-going VCC transients (glitches). It is essential that good

filtering of VCC be done to ensure that the brownout feature works correctly. Power supply decoupling is vital

even in battery powered systems.

Refer to the device specifications for the actual Vbor voltage.

Under no circumstances should the RESET pin be allowed to float. If the external Reset feature is not being

used, the RESET pin should be connected directly to VCC. The RESET input may also be connected to an

external pull-up resistor or to other external circuitry. The output of the brownout reset detector will always preset

the Idle Timer to a value between 00F0 and 00FF (240 to 256 tC). At this time, the internal reset will be

generated.

The contents of data registers and RAM are unknown following the on-chip reset.

Figure 10. Brownout Reset Operation

Figure 11. Reset Circuit Using Power-On Reset

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