LM98714 datasheet(13/115 Pages) TI1

13 / 115 page

LM98714

www.ti.com

SNAS254A – OCTOBER 2006 – REVISED JANUARY 2014

AC Timing Specifications (continued)

The following specifications apply for VA = VD = VR = VC = 3.3V, CL = 10pF, and fINCLK = 15MHz unless otherwise specified.

Boldface limits apply for TA = TMIN to TMAX; all other limits TA = 25°C.

Symbol

Parameter

Conditions

Min

Typ(1)

Max

Units

CMOS Output Timing Specifications

fINCLK = 45MHz

CLKOUT Rising Edge to CMOS

tCRDO

INCLK = ADCCLK

-2.83

2.7

Output Data

(ADC Rate Clock)

fINCLK = 45MHz

CLKOUT Falling Edge to CMOS

tCFDO

INCLK = ADCCLK

-2.83

2.7

Output Data

(ADC Rate Clock)

Serial Interface Timing Specifications

fSCLK <= fINCLK

INCLK = PIXCLK

15/22.5/30

MHz

(Pixel Rate Clock)

Mode 3/2/1

fSCLK

Input Clock Frequency

fSCLK <= fINCLK

INCLK = ADCCLK

45/45/30

MHz

(ADC Rate Clock)

Mode 3/2/1

SCLK Duty Cycle

50/50

tIH

Input Hold Time

tIS

Input Setup Time

tSENSC

SCLK Start Time After SEN Low

1.25

SEN High after last SCLK Rising

tSCSEN

2.82

Edge

INCLK must be active during

tSENW

SEN Pulse Width

TINCLK

serial interface commands.

tOD

Output Delay Time

14.6

tHZ

Data Output to High Z

0.5

TSCLK

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