WM8580AGEFTV datasheet(84/106 Pages) WOLFSON

84 / 106 page

WM8580A

Production Data

PD, Rev 4.9, November 2013

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

3:2

ADC_CLKSEL

ADC clock source

00 = ADCMLCK pin

01 = PLLACLK

10 = PLLBCLK

11 = MCLK pin

5:4

TX_CLKSEL

S/PDIF Transmitter clock source

00 = ADCMLCK pin

01 = PLLACLK

10 = PLLBCLK

11 = MCLK pin

CLKSEL_MAN

Clock selection auto-configuration override

0 = auto-configuration enabled

1 = auto-configuration disabled, clock configuration follows

relevant CLKSEL bits in R8 to R11.

PAIF 1

09h

2:0

PAIFRX_RATE

[2:0]

010

Master Mode LRCLK Rate

000 = 128fs

001 = 192fs

010 = 256fs

011 = 384fs

100 = 512fs

101 = 768fs

110 = 1152fs

4:3 PAIFRX_BCLKSEL

[1:0]

Master Mode BCLK Rate

00 = 64 BCLKs per LRCLK

01 = 32 BCLKs per LRCLK

10 = 16 BCLKs per LRCLK

11 = BCLK = System Clock

PAIFRXMS

PAIF Receiver Master/Slave Mode Select

0 = Slave Mode

1 = Master Mode

7:6

PAIFRXMS_

CLKSEL

PAIF Receiver Master Mode clock source

00 = MCLK pin

01 = PLLACLK

10 = PLLBCLK

11 = MCLK pin

R10

PAIF 2

0Ah

2:0

PAIFTX_RATE

[2:0]

010

Master Mode LRCLK Rate

000 = 128fs

001 = 192fs

010 = 256fs

011 = 384fs

100 = 512fs

101 = 768fs

110 = 1152fs

4:3 PAIFTX_BCLKSEL

[1:0]

Master Mode BCLKRate

00 = 64 BCLKs per LRCLK

01 = 32 BCLKs per LRCLK

10 = 16 BCLKs per LRCLK

11 = BCLK = System Clock

PAIFTXMS

PAIF Transmitter Master/Slave Mode Select:

0 = Slave Mode

1 = Master Mode

WM8580AGEFTV 데이터시트(PDF) 84 Page - Wolfson Microelectronics plc

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