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WM1811A 데이터시트(PDF) 31 Page - Wolfson Microelectronics plc

부품명 WM1811A
상세설명  Multi-Channel Audio Hub CODEC for Smartphones
PDF  328 Pages
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제조업체  WOLFSON [Wolfson Microelectronics plc]
홈페이지  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM1811A 데이터시트(HTML) 31 Page - Wolfson Microelectronics plc

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Production Data
WM1811A
w
PD, November 2013, Rev 4.1
31
SIGNAL TIMING REQUIREMENTS
SYSTEM CLOCKS & FREQUENCY LOCKED LOOP (FLL)
Figure 1 Master Clock Timing
Test Conditions
The following timing information is valid across the full range of recommended operating conditions.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNIT
Master Clock Timing (MCLK1 and MCLK2)
MCLK cycle time
TMCLKY
MCLK as input to FLL,
FLLn_REFCLK_DIV = 10, 11
25
ns
MCLK as input to FLL,
FLLn_REFCLK_DIV = 01
37
MCLK as input to FLL,
FLLn_REFCLK_DIV = 00
74
FLL not used, AIFnCLK_DIV = 1
40
FLL not used, AIFnCLK_DIV = 0
80
MCLK duty cycle
(= TMCLKH : TMCLKL)
60:40
40:60
Frequency Locked Loops (FLL1 and FLL2)
FLL Input Frequency
FLLn_REFCLK_DIV = 00
0.032
13.5
MHz
FLLn_REFCLK_DIV = 01
0.064
27
FLLn_REFCLK_DIV = 10
0.128
40
FLLn_REFCLK_DIV = 11
0.256
40
Internal Clocking
AIF1CLK frequency
12.5
MHz
AIF2CLK frequency
12.5
MHz
SYSCLK frequency
12.5
MHz



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