HM628512C Series

12

Low V

Parameter

Symbol

Min

Typ

Max

Unit

Test conditions*

3

V

V

DR

2—

—V

CS

≥ V

Data retention current

I

CCDR

—1*

4

50*

1

µAV

CS

≥ V

—1*

4

15*

2

µA

Chip deselect to data retention time

t

CDR

0

—

—

ns

See retention waveform

Operation recovery time

t

R

t

5

——

ns

Notes: 1. For L-version and 20

µA (max.) at Ta = –20 to +40°C.

2. For L-SL-version and 3

µA (max.) at Ta = –20 to +40°C.

3.

CS controls address buffer, WE buffer, OE buffer, and Din buffer. In data retention mode, Vin

levels (address,

WE, OE, I/O) can be in the high impedance state.

4. Typical values are at V

5. t

Low V

V

CC

4.5 V

2.2 V

0 V

CS

t

CDR

t

R

CS

≥ V

V

DR

Data retention mode