Pad No.

X

Y

Pad No.

X

Y

18

-325.00

-780.00

45

195.00

780.00

19

-195.00

-780.00

46

65.00

780.00

20

-65.00

-780.00

47

-65.00

780.00

21

65.00

-780.00

48

-195.00

780.00

22

195.00

-780.00

49

-325.00

780.00

23

325.00

-780.00

50

-455.00

780.00

24

455.00

-780.00

51

-585.00

780.00

25

585.00

-780.00

52

-715.00

780.00

26

715.00

-780.00

53

-845.00

780.00

27

845.00

-780.00

Pad Description

Pad No.

Pad Name

I/O

Description

1~5

Y15~Y19

O LCD driver output for segment*

6

VDD

¾ Positive power supply

7~26

Y20~Y39

O LCD driver output for segment

27

DO39

O Shift register output pad for the 40th bit data

28

DI20

I

Data input pad of shift register 2

29

DO19

O Shift register output pad for the 20th bit data

30, 31, 32

V5, V3, V2

I

LCD bias supply voltage

33

VSS

¾ Negative power supply, ground

34

VDD

¾ Positive power supply

35

CLK

I

Clock pulse input pad for the shift register

36

DI0

I

Data input pad of shift register 1

37

LOAD

I

Latching signal to latch shift register data

38

ALT

I

Alternate signal input pad for LCD driving waveform

39~53

Y0~Y14

O LCD driver output for segment*

*: For Y0~Y39, one of VDD, V2, V3 or V5 is selected as a display driving source according to the

combination of latched data level and ALT signal. Refer to the following table:

Latched Data

ALT

Display data output level

H

HV5

L

HV3

LV2

HT1602L

3

September 1, 2000