HT23C040 datasheet(6/10 Pages) HOLTEK

6 / 10 page

A.C. test condition

Output load: see figure right

Input rise and fall time: 10ns

Input pulse levels: 0.4V to 2.4V

Input and output timing reference levels:

0.8V and 2.0V (VCC=5V)

1.5V (VCC=3V)

Timing Diagrams

· Propagation delay due to address (CE/CE/OE1/OE1 and OE/OE are active)

· Propagation delay due to chip and output enable (address valid)

HT23C040

January 20, 2000

Va l i d

Ad d r e s s

D out

t CY C

t AA

Va l i d

t OH

t OE

t AC E

t AO E

t OD

D out

Va l i d

100p F *

V CC

1250 W

775 W

Ou t p u t

* I nc l udi ng s c ope and j i g

Output load circuit

Functional Description

The HT23C040 has two modes, namely data

read mode and standby mode, controlled by

CE/CE/OE1/OE1 and OE/OE/NC inputs.

· Standby mode

The HT23C040 has lower current consumption,

controlled by the chip enable input (CE/CE).

When a low/high level is applied to the CE/CE

input regardless of the output enable

(OE/OE/NC) states, the chip will enter the

standby mode.

· Data read mode

When both the chip enable (CE/CE/OE1/OE1)

and the output enable (OE/OE/NC) are active,

the chip is in data read mode. Otherwise, ac-

tive CE/CE and inactive OE/OE/NC result in

deselect mode. The output will remain in Hi-Z

state.

HT23C040 데이터시트(PDF) 6 Page - Holtek Semiconductor Inc

HT23C040 데이터시트(HTML) 6 Page - Holtek Semiconductor Inc

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