HT827A0 datasheet(13/49 Pages) HOLTEK

13 / 49 page

HT827A0

March 15, 2000

stack and then branching to subroutines at the

specified location(s) in the program memory.

Only the program counter is pushed onto the

stack. The programmer must save the contents

of the register or status register (STATUS) in

advance if they are altered by an interrupt ser-

vice program which corrupts the desired con-

trol sequence.

External interrupts are triggered by a high to

low transition of INT. The related interrupt re-

quest flag (EIF; bit 4 of INTC) are also set.

When an interrupt is enabled, the stack is not

full and the external interrupt is active, a sub-

routine call to location 04H will occur. The in-

terrupt request flag (EIF) and EMI bits will be

cleared to disable other interrupts.

The sampling rate counter interrupt is initial-

ized by setting a sampling rate counter inter-

rupt request flag (SRF; bit 5 of INTC), which is

caused by a timer overflow. When an interrupt

is enabled, the stack is not full and the SRF bit

is set, a subroutine call to location 08H will oc-

cur. The related interrupt request flag (SRF)

will be reset and the EMI bit be cleared to dis-

able further interrupts.

The internal timer/event counter interrupt is

initialized by setting a timer/event counter in-

terrupt request flag (TF; bit 6 of INTC), which

is caused by a timer overflow. When an inter-

rupt is enabled, the stack is not full and the TF

bit is set, a subroutine call to location 0CH will

occur. The related interrupt request flag (TF)

will be reset and the EMI bit will be cleared to

disable further interrupts.

During the execution of an interrupt subrou-

tine, other interrupt acknowledgments are all

held until the ²RETI² instruction is executed or

the EMI bit and the related interrupt control

bit are set to 1 (if the stack is not full). To return

from an interrupt subroutine, ²RET² or ²RETI²

may be invoked. RETI will set the EMI bit to

enable an interrupt service, but RET will not.

Interrupts occurring in an interval between the

rising edges of two consecutive T2 pulses will be

serviced at the latter of the two T2 pulses if the

corresponding interrupts are enabled. In the

case of simultaneous requests, they can be

masked by resetting the EMI bit. The following

table illustrates the priority of applying the si-

multaneous requests:

Bit No.

Label

Function

INTC

(0BH)

EMI

Controls a master (global) interrupt

(1=enabled; 0=disabled)

EEI

Controls an external interrupt

(1=enabled; 0=disabled)

ESI

Controls a sampling rate counter interrupt

(1=enabled; 0=disabled)

ETI

Controls a timer/event counter interrupt

(1=enabled; 0=disabled)

EIF

External interrupt request flag

(1=active; 0=inactive)

SRF

Sampling rate counter request flag

(1=active; 0=inactive)

6TF

Internal timer/event counter request flag

(1=active; 0=inactive)

Unused bit, read as ²0²

INTC register

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