AT90PWM2 datasheet(83/365 Pages) ATMEL

83 / 365 page

4317K–AVR–03/2013

AT90PWM2/3/2B/3B

Note:

1. n = 3, 2, 1 or 0.

When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt

Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed.

12.0.2

External Interrupt Mask Register – EIMSK

• Bits 3..0 – INT3 – INT0: External Interrupt Request 3 - 0 Enable

When an INT3 – INT0 bit is written to one and the I-bit in the Status Register (SREG) is set

(one), the corresponding external pin interrupt is enabled. The Interrupt Sense Control bits in the

External Interrupt Control Register – EICRA – defines whether the external interrupt is activated

on rising or falling edge or level sensed. Activity on any of these pins will trigger an interrupt

request even if the pin is enabled as an output. This provides a way of generating a software

interrupt.

12.0.3

External Interrupt Flag Register – EIFR

• Bits 3..0 – INTF3 - INTF0: External Interrupt Flags 3 - 0

When an edge or logic change on the INT3:0 pin triggers an interrupt request, INTF3:0 becomes

set (one). If the I-bit in SREG and the corresponding interrupt enable bit, INT3:0 in EIMSK, are

set (one), the MCU will jump to the interrupt vector. The flag is cleared when the interrupt routine

is executed. Alternatively, the flag can be cleared by writing a logical one to it. These flags are

always cleared when INT3:0 are configured as level interrupt.

Bit

76543210

----

INT3

INT2

INT1

IINT0

EIMSK

Read/Write

R/W

Initial Value

00000000

Bit

76543210

----

INTF3

INTF2

INTF1

IINTF0

EIFR

Read/Write

R/W

Initial Value

00000000

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