AT90PWM2 datasheet(128/365 Pages) ATMEL

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4317K–AVR–03/2013

AT90PWM2/3/2B/3B

If external pin modes are used for the Timer/Countern, transitions on the Tn pin will clock the

counter even if the pin is configured as an output. This feature allows software control of the

counting.

15.10.3

Timer/Counter1 Control Register C – TCCR1C

• Bit 7 – FOCnA: Force Output Compare for Channel A

• Bit 6 – FOCnB: Force Output Compare for Channel B

The FOCnA/FOCnB bits are only active when the WGMn3:0 bits specifies a non-PWM mode.

However, for ensuring compatibility with future devices, these bits must be set to zero when

TCCRnA is written when operating in a PWM mode. When writing a logical one to the

FOCnA/FOCnB bit, an immediate compare match is forced on the Waveform Generation unit.

The OCnA/OCnB output is changed according to its COMnx1:0 bits setting. Note that the

FOCnA/FOCnB bits are implemented as strobes. Therefore it is the value present in the

COMnx1:0 bits that determine the effect of the forced compare.

A FOCnA/FOCnB strobe will not generate any interrupt nor will it clear the timer in Clear Timer

on Compare match (CTC) mode using OCRnA as TOP.

The FOCnA/FOCnB bits are always read as zero.

15.10.4

Timer/Counter1 – TCNT1H and TCNT1L

The two Timer/Counter I/O locations (TCNTnH and TCNTnL, combined TCNTn) give direct

access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To

ensure that both the high and low bytes are read and written simultaneously when the CPU

accesses these registers, the access is performed using an 8-bit temporary High Byte Register

(TEMP). This temporary register is shared by all the other 16-bit registers. See “Accessing 16-bit

Registers” on page 106.

Modifying the counter (TCNTn) while the counter is running introduces a risk of missing a com-

pare match between TCNTn and one of the OCRnx Registers.

Writing to the TCNTn Register blocks (removes) the compare match on the following timer clock

for all compare units.

15.10.5

Output Compare Register 1 A – OCR1AH and OCR1AL

15.10.6

Output Compare Register 1 B – OCR1BH and OCR1BL

Bit

210

FOC1A

FOC1B

–

TCCR1C

Read/Write

R/W

Initial Value

Bit

76543210

TCNT1[15:8]

TCNT1H

TCNT1[7:0]

TCNT1L

Read/Write

R/W

Initial Value

00000000

Bit

76543210

OCR1A[15:8]

OCR1AH

OCR1A[7:0]

OCR1AL

Read/Write

R/W

Initial Value

00000000

Bit

76543210

OCR1B[15:8]

OCR1BH

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