AT90PWM2 datasheet(206/365 Pages) ATMEL

206 / 365 page

206

4317K–AVR–03/2013

AT90PWM2/3/2B/3B

when the Transmit Shift Register and Transmit Buffer Register do not contain data to be trans-

mitted. When disabled, the Transmitter will no longer override the TxDn port.

This bit is available for both USART and EUSART mode.

• Bit 2 – UCSZ2: Character Size

The UCSZ2 bits combined with the UCSZ1:0 bit in UCSRC sets the number of data bits (Char-

acter SiZe) in a frame the Receiver and Transmitter use.

This bit have no effect when the EUSART mode is enabled.

• Bit 1 – RXB8: Receive Data Bit 8

RXB8 is the ninth data bit of the received character when operating with serial frames with nine

data bits. Must be read before reading the low bits from UDR.

When the EUSART mode is enable and configured in 17 bits receive mode, this bit contains the

seventeenth bit (see EUSART section).

• Bit 0 – TXB8: Transmit Data Bit 8

TXB8 is the ninth data bit in the character to be transmitted when operating with serial frames

with nine data bits. Must be written before writing the low bits to UDR.

When the EUSART mode is enable and configured in 17 bits transmit mode, this bit contains the

seventeenth bit (See EUSART section).

18.10.4

USART Control and Status Register C – UCSRC

• Bit 7 – Reserved Bit

This bit is reserved for future use. For compatibilty with future devices, this bit must be written to

zero when USCRC is written.

• Bit 6 – UMSEL: USART Mode Select

This bit selects between asynchronous and synchronous mode of operation.

When configured in EUSART mode, the synchronous mode should not be set with Manchester

mode (See EUSART section).

• Bit 5:4 – UPM1:0: Parity Mode

These bits enable and set type of parity generation and check. If enabled, the Transmitter will

automatically generate and send the parity of the transmitted data bits within each frame. The

Receiver will generate a parity value for the incoming data and compare it to the UPM setting. If

a mismatch is detected, the UPE Flag in UCSRA will be set.

Bit

76543210

UMSEL0

UPM1

UPM0

USBS

UCSZ1

UCSZ0

UCPOL

UCSRC

Read/Write

R/W

Initial Value

00000110

Table 18-4.

UMSEL Bit Settings

UMSEL

Mode

Asynchronous Operation

Synchronous Operation

AT90PWM2 데이터시트(PDF) 206 Page - ATMEL Corporation

AT90PWM2 데이터시트(HTML) 206 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL