AT90PWM2 datasheet(254/365 Pages) ATMEL

254 / 365 page

254

4317K–AVR–03/2013

AT90PWM2/3/2B/3B

AT90PWM2B/3B:

On PWM2B/3B, the amplifier has been improved in order to speed-up the conversion time.The

proposed improvement takes advantage of the amplifier characteristics to ensure a conversion

in less time.

In order to have a better understanding of the functioning of the amplifier synchronization, a tim-

ing diagram example is shown Figure for AT90PWM2B/3B.

As soon as a conversion is requested thanks to the ADSC bit, the Analog to Digital Conversion

is started. In case the amplifier output is modified during the sample phase of the ADC, the on-

going conversion is aborted and restarted as soon as the output of the amplifier is stable. This

ensure a fast response time. The only precaution to take is to be sure that the trig signal (PSC)

frequency is lower than ADCclk/4.

Figure 21-16. Amplifier synchronization timing diagram for AT90PWM2B/3B

With change on analog input signal

Figure 21-17. Amplifier synchronization timing diagram for AT90PWM2B/3B

ADSC is set when the amplifier output is changing due to the amplifier clock

switch.

Valid sample

Delta V

4th stable sample

Signal to be

measured

AMPLI_clk

(Sync Clock)

CK ADC

PSCn_ASY

PSC

Block

ADSC

ADC

Activity

ADC

Sampling

ADC

Conv

ADC

Sampling

ADC

Conv

ADCResult

Ready

ADCResult

Ready

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