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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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SAM4L 데이터시트(PDF) 39 Page - ATMEL Corporation |
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SAM4L 데이터시트(HTML) 39 Page - ATMEL Corporation |
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39 / 176 page  39 42023GS–SAM–03/2014 ATSAM4L8/L4/L2 4.6 Cortex-M4 implementations options This table provides the specific configuration options implemented in the SAM4L series Table 4-1. Cortex-M4 implementation options 4.7 Cortex-M4 Interrupts map The table below shows how the interrupt request signals are connected to the NVIC. Option Implementation Inclusion of MPU yes Inclusion of FPU No Number of interrupts 80 Number of priority bits 4 Inclusion of the WIC No Embedded Trace Macrocell No Sleep mode instruction Only WFI supported Endianness Little Endian Bit-banding No SysTick timer Yes Register reset values No Table 4-2. Interrupt Request Signal Map (Sheet 1 of 3) Line Module Signal 0 Flash Controller HFLASHC 1 Peripheral DMA Controller PDCA 0 2 Peripheral DMA Controller PDCA 1 3 Peripheral DMA Controller PDCA 2 4 Peripheral DMA Controller PDCA 3 5 Peripheral DMA Controller PDCA 4 6 Peripheral DMA Controller PDCA 5 7 Peripheral DMA Controller PDCA 6 8 Peripheral DMA Controller PDCA 7 9 Peripheral DMA Controller PDCA 8 10 Peripheral DMA Controller PDCA 9 11 Peripheral DMA Controller PDCA 10 |
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