8XC196NT

Test Conditions Capacitance Load on All Pins e 100 pF Rise and Fall Times e 10 ns

The 8XC196NT will meet these specifications

Symbol

Parameter

Min

Max

Units

Frequency on XTAL1

40

20

50

250

ns

XTAL1 High to CLKOUT High or Low

a

20

110

ns

440

m

s

CLKOUT Period

ns

CLKOUT High Period

ns

CLKOUT Low to ALEADV High

b

10

a

15

ns

ALEADV Low to CLKOUT High

b

25

a

15

ns

ALEADV Cycle Time

ALEADV High Time

ns

Address Valid to ALE Low

ns

Address Hold After ALEADV Low

ns

ALEADV Low to RD Low

ns

RD Low to CLKOUT Low

b

5

a

35

ns

RD Low Period

RD High to ALEADV High

RD Low to Address Float

a

5ns

ALEADV Low to WR Low

ns

CLKOUT Low to WR Low

b

10

a

25

ns

Data Valid before WR High

ns

CLKOUT High to WR High

b

10

a

15

ns

WR Low Period

Data Hold after WR High

ns

WR High to ALEADV High

BHE INST Hold after WR High

ns

AD8 – 15 Hold after WR High

BHE INST Hold after RD High

ns

AD8 – 15 Hold after RD High

NOTES

1 Testing performed at 80 MHz however the device is static by design and will typically operate below 1 Hz

2 Typical specifications not guaranteed

3 Assuming back-to-back bus cycles

4 8-bit bus only

programming the UPROM location 0778H with the value 0004H NTNQ customer QROM codes need to equate location

2016H to the value 0CDEH if the oscillator fail detect (OFD) function is desired Intel manufacturing uses location 2016H

as a flag to determine whether or not to program the Clock Detect Enable (CDE) bit Programming the CDE bit

enables oscillator fail detection

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