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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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GMS87C4060 데이터시트(PDF) 89 Page - Hynix Semiconductor |
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GMS87C4060 데이터시트(HTML) 89 Page - Hynix Semiconductor |
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89 / 102 page  PRELIMINARY GMS81C4040/87C4060 Nov. 1999 Ver 1.0 PRELIMINARY 85 *1: Low = Input Low Voltage = VIL(<0.8V) *2: High = Input High Value = VIL(>2.0V) *3: In Gang Write Mode, All OTPs are programmed sim- ulaneously. So all signals of OTPs are in the same condi- tion *4: In Gang Verify mode, the VPP pin can be sset to both normal high(5V), aand 12.75V and chip slecection is pos- sible using the CEB pin Figure 23-4 Figure AC Programming Characteristics Limits SYMBOL Parameter Min Typ Max Unit Conditions tAS Address Setup Time 2 µs tOES OEB Setup Time 2 µs tDS Data Setup Time 2 µs tAH Address Hold Time 0 µs tDH Data Hold Time 2 µs tDFP OEB High to Output Float Delay 0 130 ns Note1 tVPS Vpp Setup Time 2 µs tCES CEB Setup Time 2 µs tPW PGMB initial program pulse width 95 100 105 µs Quick pulse programming tOE Data Valid from OEB 100 ns tACC Address to output delay 150 ns tOH output hold from addresses CEB or OEB whichever occurrs first 00 ns tCE CEB to output delay 100 ns tCS chip selection interval (@Gang verify) 100 ns *Note1: Output Float is defined as the point where data is no longer driven |
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