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STAC9704 데이터시트(PDF) 45 Page - Hynix Semiconductor

부품명 STAC9704
상세설명  Multimedia Audio Codec for AC97
PDF  49 Pages
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제조업체  HYNIX [Hynix Semiconductor]
홈페이지  http://www.skhynix.com/kor/main.do
Logo HYNIX - Hynix Semiconductor

STAC9704 데이터시트(HTML) 45 Page - Hynix Semiconductor

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SigmaTel, Inc.
STAC9704/7
45
10/02/98
Appendix A
SPLIT INDEPENDENT POWER SUPPLY OPERATION
In PC applications, one power supply input to the STAC9704/7 may be derived from a supply regulator (as shown
in Figure 3) and the other directly from the PCI power supply bus. When power is applied to the PC, the
regulated supply input to the IC will be applied some time delay after the PCI power supply. Without proper on-
chip partitioning of the analog and digital circuitry, some manufacturer’s codecs would be subject to on-chip SCR
type latch-up.
SigmaTel’s STAC9704/7 specifically allows power-up sequencing delays between the analog (AVddx) and
digital (VDddx) supply pins. These two power supplies can power-up independently and at different rates with
no adverse effects to the codec. The IC is designed with independent analog and digital circuitry that prevents
on-chip SCR type latch-up.
VIDEO_L
VIDEO_R
AUX_L
AFILT1
AFILT2
AVss1
AVss2
DVss1
DVss2
AVdd1
AVdd2
DVdd1
DVdd2
0.1uF
10uF
10uF
0.1uF
0.1uF
0.1uF
560 to 1000 pF
560 to 1000 pF
29
30
14
17
16
25
38
1
9
7
4
42
26
3
2
CAP2
XTL_OUT
XTL_IN
3.3V or 5V +/-10%
24.576MHz
32
0.1uF
10uF
SI GMATEL
STAC9704 /7
28
Vrefout
Vref
27
10uF
0.1uF
33pF
33pF
LINE_OUT_L
LINE_OUT_R
MONO_OUT
35
36
37
LINE_IN_R
24
LINE_IN_L
23
PHONE
13
P C
_ B E E P
12
MIC2
22
AUX_R
15
MIC1
21
6
5
8
11
10
SDATA_OUT
SDATA_IN
RESET
SYNC
BIT_CLK
CD_GND
CD_R
20
19
18
CD_L
Brd Analog Gnd
Brd Digital Gnd
NOTE: Pins 31, 33, 34, 40,
43 - 48 are No Connects
** Teminate ground
plane as close to power
supply as possible
LNLVL_OUT_L
LNLVL_OUT_R
39
41
reg
3.3V or 5V +/-10%
*AVdd must always be >= DVdd



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