ICS513

LOCO™ PLL Clock Generator

MDS 513 B

4

Revision 080699

Printed 12/4/00

Integrated Circuit Systems • 525 Race Street • San Jose • CA• 95126 • (408)295-9800tel• (408)295-9818fax

While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its

use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is

intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary

environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does

not authorize or warrant any ICS product for use in life support devices or critical medical instruments.

Package Outline and Package Dimensions

Inches

Inches

Millimeters

Millimeters

Symbol

Min

Max

Min

Max

A

0.055

0.068

1.397

1.7272

b

0.013

0.019

0.330

0.483

D

0.185

0.200

4.699

5.080

E

0.150

0.160

3.810

4.064

H

0.225

0.245

5.715

6.223

e

.050 BSC

.050 BSC

1.27 BSC

1.27 BSC

h

0.015

0.381

L

0.016

0.035

0.406

0.889

Q

0.004

0.01

0.102

0.254

8 pin SOIC

Ordering Information

Part/Order Number

Marking

Package

Temperature

ICS513M

ICS513M

8 pin SOIC

0-70°C

ICS513MT

ICS513M

8 pin SOIC on tape and reel

0-70°C

External Components / Crystal Selection

The ICS513 requires a 0.01µF decoupling capacitor to be connected between VDD and GND. It must be

connected close to the ICS513 to minimize lead inductance. No external power supply filtering is required

for this device. A 33

Ω terminating resistor can be used next to the CLK and REF pins. The total on-chip

capacitance is approximately 12 pF, so a parallel resonant, fundamental mode crystal should be used. For

crystals with a specified load capacitance greater than 12 pF, crystal capacitors should be connected from

each of the pins X1 and X2 to Ground as shown in the Block Diagram on page 1. The value (in pF) of

these crystal caps should be = (CL-12)*2, where CL is the crystal load capacitance in pF. These external

capacitors are only required for applications where the exact frequency is critical. For a clock input,

connect to X1 and leave X2 unconnected (no capacitors on either).

c

A

b

D

E

H

e

h x 45°

Q

Pin 1

LOCO is a trademark of ICS

L