ICS527-01

Clock Slicer™

User Configurable Zero Delay Buffer

MDS 527-01 B

4

Revision 020801

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA•95126•(408)295-9800tel • www.icst.com

FB frequency = Input frequency •

(FDW+2)

(RDW+2)

Determining (setting) the ICS527-01 Dividers

The user has full control in setting the desired output clocks over the range shown in the table on page 2. The

user should connect the divider select input pins directly to ground (or VDD, although this is not required

because of internal pull-ups) during Printed Circuit Board layout, so that the ICS527-01 automatically

produces the correct clock when all components are soldered. It is also possible to connect the inputs to

parallel I/O ports to switch frequencies.

The dividers are expressed as integers. For example, if a 50 MHz output on CLK1 is desired from a

40 MHz input, the reference divider word (RDW) should be 2 and the feedback divider (FDW) should be

3 which gives the required 5/4 multiplication. If multiple choices of divider are available, then the lowest

numbers should be used. In this example, the output divide (OD) should be selected to be 2. Then R6:R0

is 0000010, F6:F0 is 0000011 and S1:S0 is 00. Also, this example assumes CLK1 is connected to FBIN.

You may also fax this page to MicroClock/ICS at 408 295-9818, or send an e-mail to ics-mk@icst.com.

Be sure to indicate the following:

Your Name ________________ Company Name___________________ Telephone_________________

Respond by e-mail (list your e-mail address) __________________or fax number ___________________

Desired input clock (in MHz) _______________ Desired output frequency________________

Also, the following operating ranges should be observed:

300 kHz <

Input Frequency

(RDW+2)

Where Reference Divider Word (RDW) = 0 to 127

Feedback Divider Word (FDW) = 0 to 127

FB frequency is the same as either CLK1 or CLK2 depending on

feedback connection

The output of the ICS527-01 can be determined by the following simple equation:

The output divide should be selected depending on the frequency of CLK1.

The table on page 2 gives the ranges.