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ICS543 데이터시트(PDF) 3 Page - Integrated Circuit Systems

부품명 ICS543
상세설명  PRELIMINARY INFORMATION Clock Divider and 2X Multiplier
PDF  4 Pages
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제조업체  ICST [Integrated Circuit Systems]
홈페이지  http://www.icst.com
Logo ICST - Integrated Circuit Systems

ICS543 데이터시트(HTML) 3 Page - Integrated Circuit Systems

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ICS543
Clock Divider and 2X Multiplier
MDS 543 A
3
Revision 010599
Printed 12/4/00
Integrated Circuit Systems, Inc.•525 Race Street•San Jose•CA•95126•(408)295-9800tel•(408)295-9818fax
I C R O
C LOC K
PRELIMINARY INFORMATION
Electrical Specifications
Parameter
Conditions
Minimum
Typical
Maximum
Units
ABSOLUTE MAXIMUM RATINGS (stresses beyond these can permanently damage the device)
ABSOLUTE MAXIMUM RATINGS (stresses beyond these can permanently damage the device)
ABSOLUTE MAXIMUM RATINGS (stresses beyond these can permanently damage the device)
ABSOLUTE MAXIMUM RATINGS (stresses beyond these can permanently damage the device)
Supply Voltage, VDD
Referenced to GND
7
V
Inputs
Referenced to GND
-0.5
VDD+0.5
V
Clock Output
Referenced to GND
-0.5
VDD+0.5
V
Ambient Operating Temperature
0
70
C
Soldering Temperature
Max of 10 seconds
260
C
Storage temperature
-65
150
C
DC CHARACTERISTICS (VDD = 5.0V unless otherwise noted)
DC CHARACTERISTICS (VDD = 5.0V unless otherwise noted)
Operating Voltage, VDD
3
5.5
V
Input High Voltage, VIH, ICLK only
ICLK (Pin 1)
(VDD/2)+1
VDD/2
V
Input Low Voltage, VIL, ICLK only
ICLK (Pin 1)
VDD/2
(VDD/2)-1
V
Input High Voltage, VIH
S0, S1, OE
2
V
Input Low Voltage, VIL
S0, S1, OE
0.8
V
Output High Voltage, VOH
IOH=-25mA
2.4
V
Output Low Voltage, VOL
IOL=25mA
0.4
V
IDD Operating Supply Current, 50 MHz input
No Load, 5.0V, ÷5, ÷10
17
mA
IDD Operating Supply Current, 50 MHz input
No Load, 3.3V, ÷5, 10
9
mA
Short Circuit Current
Each Output
±70
mA
Input Capacitance, S1, S0, OE
Pins 4, 5, 6
4
pF
AC CHARACTERISTICS (VDD = 5.0V unless otherwise noted)
AC CHARACTERISTICS (VDD = 5.0V unless otherwise noted)
Input Frequency, clock input
at VDD = 5V
4
See page 2
MHz
Input Frequency, clock input
at VDD = 3.3V
4
See page 2
MHz
Skew of output clocks
rising edges at VDD/2
500
ps
Output Clock Rise Time
0.8 to 2.0V
1
ns
Output Clock Fall Time
2.0 to 0.8V
1
ns
Output Clock Duty Cycle
at VDD/2
45
49 to 51
55
%



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