ICS551

1 to 4 Clock Buffer

MDS 551 B

2

Revision 091200

Printed 11/14/00

Integrated Circuit Systems, Inc.•525 Race Street•San Jose•CA•95126•(408)295-9800tel•(408)295-9818fax

PRELIMINARY INFORMATION

Pin Assignment

Number

Name

Type

Description

1

ICLK

CI

Clock input. Internal pull-up resistor.

2

Q1

O

Clock Output 1.

3

Q2

O

Clock Output 2.

4

Q3

O

Clock Output 3.

5

Q4

O

Clock Output 4.

6

GND

P

Connect to ground.

7

VDD

P

Connect to +3.3 V or +5.0 V.

8

OE

I

Output Enable. Tri-states outputs when low. Internal pull-up resistor.

Pin Descriptions

Key: CI = clock input, I = input, O = output, P = power supply connection

1

8

2

3

4

7

6

5

ICLK

Q2

OE

Q1

Q4

8 pin SOIC

Q3

VDD

GND

External Components

A minimum number of external components are required for proper operation. A decoupling capacitor of

0.01 µF should be connected between VDD on pin 7 and GND on pin 6, and a 33

Ω terminating resistor

may be used on each clock output if the trace is longer than 1 inch.