5

ICS9147- 01

Notes:

1. All timing is referenced to the Internal CPU clock (defined as inside the ICS9147 device).

2. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside the ICS9147.

3. The shaded sections on the VCO and the Crystal signals indicate an active clock is being generated.

The power down selection is used to put the part into a very low power state without turning off the power to the part.

PD# is an asynchronous active low input. This signal is synchronized internal by the ICS9147-01 prior to its control

action of powering down the clock synthesizer. PD# is an asynchronous function for powering up the system. Internal

clocks will not be running after the device is put in power down state. When PD# is active (low) all clocks are driven to

a low state and held prior to turning off the VCOs and the Crystal oscillator. The power on latency is guaranteed to be

less than 3mS. The power down latency is less than three CPU clock cycles. BUSSTOP# and CPUSTOP# are don’t care

signals during the power down operations.

PD# Timing Diagram

Notes:

1. All timing is referenced to the Internal BUS clock (defined as inside the ICS9147 device.)

2. BUSSTOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be

synchronized inside the ICS9147.

3. All other clocks continue to run undisturbed.

4. PD# and CPUSTOP# are shown in a high (true) state.