2

ICS9147-06

Pin Descriptions

Functionality

PD#

BUSEN

CPUEN

FS1

FS0

CPU (1:4)

CPUH

BUS

REF

IOAPIC

24

(MHz)

48

(MHz)

11100

Tristate

Tristate

Tristate

Tristate

Tristate

11101

60

30

14.31818

24

48

11110

66.6

33.3

14.31818

24

48

11111

REF/2

REF/4

REF

REF/4

REF/2

1

1

0

X

X

LOW

Running

14.31818

24

48

1

0

1

X

X

Running

LOW

14.31818

24

48

0

XXXX

LOW

LOW

LOW

LOW

LOW

PIN NUMBER

PIN NAME

TYPE

DESCRIPTION

1, 2, 47

REF1, REF2, REF3

OUT

14.318 MHz reference clock outputs.

3, 10, 18, 24, 30, 32,

37, 43, 44

GND

PWR

Ground.

4X1

IN

Crystal input, has internal crystal load capacitor, and feedback resistor

from X2. Nominally 14.31818MHz.

5

X2

OUT

Crystal output, has internal crystal load capacitor

8, 9, 11, 12, 13, 14,

16, 17

BUS (1:8)

OUT

BUS clock outputs, operates synchronously at CPU/2.

26, 27

FS (0:1)

IN

Select pin for enabling CPU and BUS clock frequencies.*

7, 15, 21, 25, 34, 48

VDD3

PWR

Core and Buffer output clock power supply.

22, 23

48M (1:2)

OUT

48 MHz clock output

28

PD#

IN

Device power down input, stops outputs low and shuts off crystal

oscillator and PLLs when low.*

29

CPUEN

IN

Output enable for all CPU clocks, a logic low will Stop low all CPU

clocks.*

36

CPUH

OUT

3.3 (VDD3 dependent) CPU clock output

38, 39, 41, 42

CPU (1:4)

OUT

CPU clock output clocks, operates at VDDL supply voltage (with

IOAPIC), either nominal 3.3V VDD or reduced voltage 2.9 to 2.5V.

6BUSEN

IN

Output enable for all BUS clock, a logic low will stop Low all Bus

clocks.*

45

IOAPIC

OUT

IOAPIC clock output. (14.318 MHz), operates at VDDL supply voltage

with CPU (1:4), either nominal 3.3V VDD or reduced voltage

2.9 to 2.5V.

40, 46

VDDL

PWR

Power supply for CPU and IOAPIC block buffers, operates at nominal

3.3V VDD or reduced voltage 2.9 to 2.5V.

33

24M

OUT

24 MHz clock output