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ICS9176-01 데이터시트(PDF) 3 Page - Integrated Circuit Systems |
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ICS9176-01 데이터시트(HTML) 3 Page - Integrated Circuit Systems |
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3 / 8 page ![]() 3 ICS9176-01 Timing Diagrams Note: In test mode, the VCOs are bypassed. The test clock input is simply buffered, then output. The part is transparent. Damage to the device may occur if an output is shorted or forced to ground or VDD. Timing in Power-down Mode Timing in Eliminate by Test Mode Timing in Divide by 2 Mode Timing in Divide by 1 Mode |
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