3

ICS9178-03

Pin Description

*=Pin is pulled-up to VDD internally by the device.

PIN NUMBER

PIN NAME

TYPE

DESCRIPTION

32

XAS0

Input

LSB Programmable Group A frequency selector.

31

XAS1

Input

MSB Programmable Group A frequency selector.

6

XCLKA0

Output

TTL/CMOS group A programmable clock output.

5

XCLKA1

Output

TTL/CMOS group A programmable clock output.

30

XBS0

Input

LSB Programmable Group B frequency selector.

29

XBS1

Input

MSB Programmable Group B frequency selector.

3

XCLKB0

Output

TTL/CMOS Group B programmable clock output.

2

XCLKB1

Output

TTL/CMOS Group B programmable clock output.

1

VDDXBA

—

Power for programmable Group A and B buffers (Pins 2, 3, 5, 6).

4

GNDXBA

—

Ground for programmable Group A and B buffers (Pins 2, 3, 5, 6).

44

GNDXC

—

Ground for the programmable Group C buffers (Pins 42 and 43).

43

XCLKC0

Output

TTL/CMOS Group C programmable clock output.

42

XCLKC1

Output

TTL/CMOS Group C programmable clock output.

41

VDDXC

—

Power for the XC signal output buffers (Pins 42 and 43).

28

XCS0

Input

LSB Programmable Group C frequency selector.

27

XCS1

Input

MSB Programmable Group C frequency selector.

11

PCLK0

Output

TTL/CMOS 1X Processor clock output.

10

PCLK1

Output

TTL/CMOS 1X Processor clock output.

8

GNDP

—

Ground for PCLK output buffers (Pins 11 and 10).

7

VDDP

—

Power for PCLK output buffers (Pins 11 and 10).

22

2XPCLK0

Output

PECL 2X Processor clock output.

21

2XPCLK1

Output

PECL 2X Processor clock output.

24

EVDD

—

Power for PECL buffers (Pins 21 and 22).

23

EGND

—

Ground for PECL buffers (Pins 21 and 22).

20

EGND

—

Ground for PECL buffers (Pins 21 and 22).

38*

FS0

Input

LSB frequency select PLL (divider mode control).

37*

FS1

Input

MSB frequency select PLL (divider mode control).

36

FBCLK

Input

External PLL feedback path from one of the BCLK outputs.

35

REFCLK

Input

External reference clock input.

25

AVDD

—

Power for the analog PLL circuitry.

26

AGND

—

Ground for the analog PLL circuitry.

19

DCLK

Output

TTL/CMOS D clock output.

16

VDDD

—

Power for D output buffers (Pin 19).

17

GNDD

—

Ground for D output buffer (Pin 19).

15

BCLK0

Output

TTL/CMOS B (Bus) clock output.

14

BCLK1

Output

TTL/CMOS B (Bus) clock output.

13

GNDBAB

—

Ground for output buffers AB and B clocks (Pins 14, 15 & 18).

12

VDDBAB

—

Power for output buffers AB and B clocks (Pins 14, 15 & 18).

18

ABCLK

Output

TTL/CMOS AB Bus clock (has Asymmetric duty cycle).

40

TCLK

Input

External test clock input.

39

TEN#

Input

Test enable (tie low).

9

RESET#

Input

Sync register reset (active low).

33

VDD

—

Digital power supply for 5.0 or 3.3V.

34

GND

—

Digital ground supply.