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IDT74FCT299ASOB 데이터시트(PDF) 2 Page - Integrated Device Technology

부품명 IDT74FCT299ASOB
상세설명  FAST CMOS 8-INPUT UNIVERSAL SHIFT REGISTER
PDF  7 Pages
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제조업체  IDT [Integrated Device Technology]
홈페이지  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT74FCT299ASOB 데이터시트(HTML) 2 Page - Integrated Device Technology

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IDT54/74FCT299/A/C
FAST CMOS 8-INPUT UNIVERSAL SHIFT REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
7.11
2
PIN CONFIGURATIONS
DIP/SOIC/CERPACK
TOP VIEW
LCC
TOP VIEW
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Rating
Commercial
Military
Unit
VTERM
(2) Terminal Voltage
–0.5 to +7.0
–0.5 to +7.0
V
with Respect
to GND
VTERM
(3) Terminal Voltage
–0.5 to VCC
–0.5 to VCC
V
with Respect
to GND
TA
Operating
0 to +70
–55 to +125
°C
Temperature
TBIAS
Temperature
–55 to +125
–65 to +135
°C
Under Bias
TSTG
Storage
–55 to +125
–65 to +150
°C
Temperature
PT
Power Dissipation
0.5
0.5
W
IOUT
DC Output Current
120
120
mA
NOTES:
2561 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied.
Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed Vcc by +0.5 unless otherwise noted.
2. Inputs and VCC terminals only.
3. Outputs and I/O terminals only.
CAPACITANCE (TA = +25
°C, f = 1.0MHz)
Symbol
Parameter
(1)
Conditions
Typ. Max. Unit
CIN
Input Capacitance
VIN = 0V
6
10
pF
CI/O
I/O Capacitance
VOUT = 0V
8
12
pF
NOTE:
2561 tbl 04
1. This parameter is guaranteed by characterization data and not tested.
FUNCTION TABLE
(1)
Inputs
MR
MR S1
S0
CP
Response
L
X
X
X
Asynchronous Reset Q0–Q7 = LOW
HH
H
↑ Parallel Load; I/On → Qn
HL
H
↑ Shift Right; DS0 → Q0, Q0 → Q1, etc.
HH
L
↑ Shift Left; DS7 → Q7, Q7→ Q6, etc.
H
L
L
X
Hold
NOTE:
2561 tbl 02
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
↑ = LOW-to-HIGH clock transition
5
6
7
8
S0
OE1
1
2
3
4
20
19
18
17
16
15
14
13
Vcc
P20-1
D20-1
S020-2
&
E20-1
OE2
I/O6
I/O4
I/O2
GND
S1
DS7
Q7
I/O7
I/O5
I/O
I/O1
I/O0
Q0
MR
9
10
12
11
3
CP
DS0
PIN DESCRIPTION
Pin Names
Description
CP
Clock Pulse Input (Active Edge Rising)
DS0
Serial Data Input for Right Shift
DS7
Serial Data Input for Left Shift
S0, S1
Mode Select Inputs
MR
Asynchronous Master Reset Input (Active LOW)
OE1, OE2
3-State Output Enable Inputs (Active LOW)
I/O0–I/O7
Parallel Data Inputs or 3-State Parallel Outputs
Q0, Q7
Serial Outputs
2561 tbl 01
4
5
6
7
8
L20-2
18
17
16
15
14
INDEX
2561 drw 02
I/O6
I/O4
I/O2
I/O0
Q0
DS7
Q7
I/O7
I/O5
I/O3
9 10 11 12 13
32
1
20 19



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