28F008SA datasheet(17/33 Pages) INTEL

17 / 33 page

28F008SA

290429 – 10

Bus

Command

Comments

Operation

Write

Erase

Data e B0H

Suspend

Write

Read

Data e 70H

Status Register

Standby

Check RYBY

Read

VOH e Ready VOL e

Busy or Read Status

Check SR7

1 e Ready 0 e Busy

Toggle OE

or CE

Update Status Register

Standby

Check SR6

1 e Suspended

Write

Read Array

Data e FFH

Read

Read array data from block

other than that being

erased

Write

Erase Resume

Data e D0H

Figure 9 Erase SuspendResume Flowchart

Power Supply Decoupling

Flash memory power switching characteristics re-

quire careful device decoupling System designers

are interested in 3 supply current issues standby

current levels (ISB) active current levels (ICC) and

transient peaks produced by falling and rising edges

of CE

Transient current magnitudes depend on

the device outputs’ capacitive and inductive loading

Two-line control and proper decoupling capacitor

selection will suppress transient voltage peaks

Each device should have a 01 mF ceramic capacitor

connected between each VCC and GND and be-

tween its VPP and GND These high frequency low

inherent-inductance capacitors should be placed as

close as possible to package leads Additionally for

every 8 devices a 47 mF electrolytic capacitor

should be placed at the array’s power supply con-

nection between VCC and GND The bulk capacitor

will overcome voltage slumps caused by PC board

trace inductances

VPP Trace on Printed Circuit Boards

Writing flash memories while they reside in the tar-

get system requires that the printed circuit board

designer pay attention to the VPP power supply

trace The VPP pin supplies the memory cell current

for writing and erasing Use similar trace widths and

layout considerations given to the VCC power bus

Adequate VPP supply traces and decoupling will de-

crease VPP voltage spikes and overshoots

28F008SA 데이터시트(PDF) 17 Page - Intel Corporation

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