82375EB datasheet(25/131 Pages) INTEL

25 / 131 page

82375EBSB

PIN NAME

Type

Description

PCEB BUFFER COHERENCY CONTROL

NMFLUSH

NEW MASTER FLUSH

The bi-directional NMFLUSH

signal provides handshake

between the PCEB and ESC to control flushing of PCI system buffers on behalf of

EISA masters

During an EISA Bus ownership change before the ESC can grant the bus to the

EISA master (or DMA) the ESC must ensure that system buffers are flushed and the

buffers pointing towards the EISA subsystem are disabled The ESC asserts

NMFLUSH

for one PCI clock to request system buffer flushing (After asserting

NMFLUSH

for 1 PCI clock the ESC tri-states NMFLUSH

) When the PCEB

samples NMFLUSH

asserted it starts immediately to assert NMFLUSH

and

begins flushing its internal buffers if necessary The PCEB also requests PCI system

buffer flushing via the MEMREQ

FLSHREQ

and MEMACK

signals

When the PCEB completes its internal buffer flushing and MEMACK

is asserted

(indicating that the PCI system buffer flushing is complete) the PCEB negates

NMFLUSH

for 1 PCI clock and stops driving it When the ESC samples

NMFLUSH

negated it grants the EISA Bus to an EISA master (or DMA) The ESC

resumes responsibility of the default NMFLUSH

driver and starts driving

NMFLUSH

negated until the next time a new EISA master (or DMA) wins

arbitration

This signal is synchronous with PCICLK and is negated by the ESC at reset

AFLUSH

APIC FLUSH

AFLUSH

is bi-directional signal between the PCEB and ESC that

controls system buffer flushing on behalf of the APIC After a reset the ESC negates

AFLUSH

until the APIC is initialized and the first interrupt request is recognized

82375EB 데이터시트(PDF) 25 Page - Intel Corporation

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