3-5

which are unique to the minimum mode are described; all other pin functions are as described above.

MINIMUM MODE SYSTEM

SYMBOL

PIN

NUMBER

TYPE

DESCRIPTION

IO/M

28

O

STATUS LINE: is an inverted maximum mode S2. It is used to distinguish a memory access from

an I/O access. IO/M becomes valid in the T4 preceding a bus cycle and remains valid until the final

T4 of the cycle (I/O = HIGH, M = LOW). IO/M is held to a high impedance logic one during local bus

“hold acknowledge”.

WR

29

O

Write: strobe indicates that the processor is performing a write memory or write I/O cycle, depend-

ing on the state of the IO/M signal. WR is active for T2, T3, and Tw of any write cycle. It is active

LOW, and is held to high impedance logic one during local bus “hold acknowledge”.

INTA

24

O

INTA: is used as a read strobe for interrupt acknowledge cycles. It is active LOW during T2, T3 and

Tw of each interrupt acknowledge cycle. Note that INTA is never floated.

ALE

25

O

ADDRESS LATCH ENABLE: is provided by the processor to latch the address into the

82C82/82C83 address latch. It is a HIGH pulse active during clock low of T1 of any bus cycle. Note

that ALE is never floated.

DT/R

27

O

DATA TRANSMIT/RECEIVE: is needed in a minimum system that desires to use an 82C86/82C87

data bus transceiver. It is used to control the direction of data flow through the transceiver. Logically,

DT/R is equivalent to S1 in the maximum mode, and its timing is the same as for IO/M (T = HIGH,

R = LOW). This signal is held to a high impedance logic one during local bus “hold acknowledge”.

DEN

26

O

DATA ENABLE: is provided as an output enable for the 82C86/82C87 in a minimum system which

uses the transceiver. DEN is active LOW during each memory and I/O access, and for INTA cycles.

For a read or INTA cycle, it is active from the middle of T2 until the middle of T4, while for a write

cycle, it is active from the beginning of T2 until the middle of T4. DEN is held to high impedance logic

one during local bus “hold acknowledge”.

HOLD,

HLDA

31

30

I

O

HOLD: indicates that another master is requesting a local bus “hold”. To be acknowledged, HOLD

must be active HIGH. The processor receiving the “hold” request will issue HLDA (HIGH) as an

acknowledgment, in the middle of a T4 or T1 clock cycle. Simultaneous with the issuance of HLDA

the processor will float the local bus and control lines. After HOLD is detected as being LOW, the

processor lowers HLDA, and when the processor needs to run another cycle, it will again drive the

local bus and control lines.

Hold is not an asynchronous input. External synchronization should be provided if the system cannot

otherwise guarantee the set up time.

SS0

34

O

STATUS LINE: is logically equivalent to S0

in the maximum mode. The combination of

SS0, IO/M and DT/R allows the system to

completely decode the current bus cycle

status. SS0 is held to high impedance logic

one during local bus “hold acknowledge”.

IO/M

DT/R

SS0

CHARACTERISTICS

1

0

0

Interrupt Acknowledge

1

0

1

Read I/O Port

1

1

0

Write I/O Port

1

1

1

Halt

0

0

0

Code Access

0

0

1

Read Memory

0

1

0

Write Memory

0

1

1

Passive

80C88