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CD40102BMS 데이터시트(PDF) 7 Page - Intersil Corporation

부품명 CD40102BMS
상세설명  CMOS 8-Stage Presettable Synchronous Down Counters
PDF  13 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  INTERSIL [Intersil Corporation]
홈페이지  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

CD40102BMS 데이터시트(HTML) 7 Page - Intersil Corporation

Back Button CD40102BMS Datasheet HTML 3Page - Intersil Corporation CD40102BMS Datasheet HTML 4Page - Intersil Corporation CD40102BMS Datasheet HTML 5Page - Intersil Corporation CD40102BMS Datasheet HTML 6Page - Intersil Corporation CD40102BMS Datasheet HTML 7Page - Intersil Corporation CD40102BMS Datasheet HTML 8Page - Intersil Corporation CD40102BMS Datasheet HTML 9Page - Intersil Corporation CD40102BMS Datasheet HTML 10Page - Intersil Corporation CD40102BMS Datasheet HTML 11Page - Intersil Corporation Next Button
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 7 / 13 page
background image
7-1300
CD40102BMS, CD40103BMS
Logic Diagrams
FIGURE 1. LOGIC DIAGRAM FOR CD40102BMS
J
Q
CI
FF1
J
Q
CI
FF2
J
Q
CI
FF3
Q
CLR
CLR
SPE
SPE
APE
CL
CL
J
CI
Q
Q
FF3
J
Q
CI
FF7
J
Q
CI
FF6
J
Q
CI
FF5
J
Q
CI
FF4
J0
45
6
7
J1
J2
J3
**
*
*
(MSB)
A
B
C
D
E
CI/CE
*
3
2
15
9
1
CLR
SPE
APE
CLOCK
*
*
*
*
TO
FF1 - FF7
TO
FF1 - FF7
J4
J5
J6
J7
10
11
12
13
(MSB)
****
A
B
C
14
CARRY OUT/
ZERO DETECT
D
E
VDD
VSS
*ALL INPUTS ARE
PROTECTED BY COS/MOS
PROTECTION NETWORK
LSD
MSD



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