7-1418

CD40182BMS

FIGURE 10. 64-BIT FULL CARRY LOOK-AHEAD ALU IN 3 LEVELS

FIGURE 11. COMBINED TWO-LEVEL LOOK-AHEAD AND RIPPLE-CARRY ALU

Cn

GP

Cn

G0 P0 Cn + x

Cn + y

Cn + z

GP

(16) CD40181BMS

CD40182BMS

Cn

GP

G1 P1

Cn

GP

G2 P2

Cn

GP

G3 P3

Cn

GP

Cn

G0 P0 Cn + x

Cn + y

Cn + z

CD40182BMS

Cn

GP

G1 P1

Cn

GP

G2 P2

Cn

GP

G3 P3

Cn

G0 P0

Cn + x

G1 P1

Cn + y

Cn

Cn

GP

G0 P0

CD40182BMS

Cn

Cn

Cn

GP

Cn

G0 P0 Cn + x

Cn + y

Cn + z

CD40182BMS

Cn

GP

G1 P1

Cn

G2 P2

Cn

G3 P3

Cn

Cn

Cn

GP

G0 P0

Cn

GP

G1 P1

Cn + x

Cn + y

CD40181BMS

Cn+4

Cn + 4

Cn + 4

GP

CD40181BMS

GP

Cn+4

Chip Dimensions and Pad Layout

The photographs and dimensions of each CMOS chip represent a chip when

it is part of the wafer. When the wafer is separated into individual chips, the an-

gle of cleavage may vary with respect to the chip face for different chips. The

actual dimensions of the isolated chip, therefore, may differ slightly from the

nominal dimensions shown. The user should consider a tolerance of -3 mils to

+16 mils applicable to the nominal dimensions shown.

Dimension in parenthesis are in millimeters and are derived from the basic inch

METALLIZATION:

Thickness: 11k

Å

PASSIVATION:

10.4kÅ - 15.6k

BOND PADS:

0.004 inches X 0.004 inches MIN

DIE THICKNESS:

0.0198 inches - 0.0218 inches