7-450

CD4071BMS, CD4072BMS, CD4075BMS

FIGURE 1. SCHEMATIC DIAGRAM FOR CD4071BMS (1 OF 4 IDENTICAL GATES)

FIGURE 2. LOGIC DIAGRAM FOR CD4071BMS (1 OF 4 IDENTICAL GATES)

FIGURE 3. SCHEMATIC DIAGRAM FOR CD4072BMS (1 OF 2 IDENTICAL GATES)

FIGURE 4. LOGIC DIAGRAM FOR CD4072BMS (1 OF 2 IDENTICAL GATES)

n

p

ALL INPUTS PROTECTED BY

*

CMOS PROTECTION NETWORK

VDD

VSS

*

1 (6, 8, 13)

n

p

*

2 (5,9, 12)

n

p

n

3 (4, 10, 11)

pp

nn

VSS

7

VDD

14

p

J

3 (4, 10, 11)

2 (5, 9, 12)

1 (6, 8, 13)

B

A

n

p

ALL INPUTS PROTECTED BY

*

CMOS PROTECTION NETWORK

VDD

VSS

*

2 (12)

n

p

n

1 (13)

p

INV 2

**

INV 3

**

INV 4

**

*

3 (11)

*

5 (9)

*

4 (10)

p

p

n

n

n

p

p

VSS

VDD

n

n

p

VDD

VDD

VDD

VSS

VSS

VSS

VSS

VDD

INV.1

**

J

1 (13)

3 (11)

2 (12)

A

B

4 (10)

5 (9)

D

C