7-1214

CD4518BMS, CD4520BMS

FIGURE 13. RIPPLE CASCADING OF FOUR COUNTERS WITH POSITIVE EDGE TRIGGERING

* For synchronous cascading, the clock transition time should be made less than or equal to the sum of the fixed propagation delay at 15pF

and the transition time of the output driver stage for the estimated capacitive load.

FIGURE 14. SYNCHRONOUS CASCADING OF FOUR BINARY COUNTERS WITH NEGATIVE EDGE TRIGGERING

456

Q1A

Q2A

Q3A

Q4A

RESET

2

CLOCK ENABLE

3

A

A

A

7

1

VDD

12

13

14

Q1B

Q2B

Q3B

Q4B

RESET

10

CLOCK ENABLE

11

B

B

B

15

9

456

Q1A

Q2A

Q3A

Q4A

RESET

2

CLOCK ENABLE

3

A

A

A

7

1

12

13

14

Q1B

Q2B

Q3B

Q4B

RESET

10

CLOCK ENABLE

11

B

B

B

15

9

CD4518BMS/20BMS

CD4518BMS/20BMS

CLOCK

INPUT

456

Q1A

Q2A

Q3A

Q4A

RESET

2

CLOCK ENABLE

3

A

A

A

3

1

12

13

14

Q1B

Q2B

Q3B

Q4B

RESET

10

CLOCK ENABLE

11

B

B

B

15

9

456

Q1A

Q2A

Q3A

Q4A

RESET

2

CLOCK ENABLE

3

A

A

A

3

1

12

13

14

Q1B

Q2B

Q3B

Q4B

RESET

10

CLOCK ENABLE

11

B

B

B

15

9

CD4520BMS

CD4520BMS

CLOCK

*

INPUT

CD4012A

CD4071

CD4071

CD4520BMS

CD4012A

CD4012A