6-5

March 1997

CDP1821C/3

High-Reliability CMOS

1024-Word x 1-Bit Static RAM

Features

• Static CMOS Silicon-On-Sapphire Circuitry CD4000-

Series Compatible

• Compatible with CDP1800-Series Microprocessors at

Maximum Speed

• Single Voltage Supply

• No Precharge or External Clocks Required

• Low Quiescent and Operating Power

• Separate Data Inputs and Outputs

• Memory Retention for Standby Battery Voltage Down

• Latch-Up-Free Transient-Radiation Tolerance

Description

The CDP1821C/3 is a 1024-word x 1-bit CMOS silicon-on-sap-

phire (SOS), fully static, random-access memory designed for

use in CDP1800 microprocessor systems. This device has a

recommended operating voltage range of 4V to 6.5V.

The output state of the CDP1821C/3 is a function of the

input address and chip-select states only. Valid data will

appear at the output in one access time following the latest

address change to a selected chip. After valid data appears,

the address may be changed immediately. It is not neces-

sary to clock the chip-select input or any other input terminal

for fully static operation; therefore the chip-select input may

be used as an additional address input. When the device is

in an unselected state (CS = 1), the internal write circuitry

and output sense amplifier are disabled. This feature allows

the three-state data outputs from many arrays to be OR-tied

to a common bus for easy memory expansion.

Pinout

CDP1821C/3

(SBDIP)

TOP VIEW

Ordering Information

PACKAGE

TEMP. RANGE

PART

NUMBER

PKG. NO.

SBDIP

CDP1821CD3

D16.3

14

15

16

9

13

12

11

10

1

2

3

4

5

7

6

8

CS

A0

A1

A2

A3

A4

DO

RD/WR

A9

A8

A7

A6

A5

DI

File Number

2983.1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

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