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FSTYC9055D 데이터시트(PDF) 8 Page - Intersil Corporation |
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FSTYC9055D 데이터시트(HTML) 8 Page - Intersil Corporation |
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8 / 8 page ![]() 8 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with- out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil Ltd. 8F-2, 96, Sec. 1, Chien-kuo North, Taipei, Taiwan 104 Republic of China TEL: 886-2-2515-8508 FAX: 886-2-2515-8369 FSTYC9055D, FSTYC9055R SMD2 3 PAD CERAMIC LEADLESS CHIP CARRIER D A D1 E1 E2 b D2 E 1 2 3 1 - GATE 2 - SOURCE 3 - DRAIN SYMBOL INCHES MILLIMETERS NOTES MIN MAX MIN MAX A 0.130 0.142 3.30 3.60 3 b 0.135 0.145 3.43 3.68 - D 0.520 0.530 13.20 13.46 - D1 0.435 0.445 11.05 11.30 - D2 0.115 0.125 2.92 3.17 - E 0.685 0.695 17.40 17.65 - E1 0.470 0.480 11.94 12.19 - E2 0.152 0.162 3.86 4.11 - NOTES: 1. No current JEDEC outline for this package. 2. Controlling dimension: INCH. 3. Measurement prior to pre-solder coating the mounting pads. 4. Revision 3 dated 5-00. |
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