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UPC1830 데이터시트(PDF) 13 Page - NEC |
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UPC1830 데이터시트(HTML) 13 Page - NEC |
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13 / 44 page ![]() µPC1830 13 5. BLOCK OPERATION 5.1 Video Signal Processing Section (1) Input signal After coupling by a capacitor (0.22 µF), a 1 Vp-p composite video signal is input to the composite video signal input pin (pin 36). (2) Clamp circuit The clamp circuit controls the pedestal voltage level to be constant to make it a reference voltage for the post-stage signal processing. (3) Chroma trap circuit Eliminates the chroma signal (NTSC system: approximately 3.58 MHz, PAL system: approximately 4.43 MHz) from a composite video signal and extracts a brightness signal. (4) Separate/composite switching circuit Operates as shown in Table 5-1 according to the voltage of the separate chroma input pin (pin 34). Table 5-1. Operation when Switching Separate/Composite Signals Separate chroma input Mode Brightness signal ACC amp input pin (pin 34) voltage processing Less than 3.7 V Y/C separate input Without chroma trap Input from separate chroma 3.7 V or higher Composite video input With chroma trap Input from chroma BPF (5) Delay circuit Compensates for the delay between the brightness signal and chroma signal by delaying the brightness signal. (6) Contrast adjustment circuit Adjusts the amplitude of the brightness signal output from the Y output pin (pin 12) according to the voltage of the contrast control pin (pin 38). The control characteristic is shown in Figure 5-1. |
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