AD9877 datasheet(13/36 Pages) AD

13 / 36 page

AD9877

Rev. B | Page 13 of 36

THEORY OF OPERATION

To gain a general understanding of the AD9877, refer to the

block diagram of the device architecture in Figure 15. The

following is a general description of the device functionality.

Later sections will detail each of the data path building blocks.

TRANSMIT SECTION

Modulation Mode Operation

The AD9877 accepts 6-bit words that are strobed synchronous

to the master clock, MCLK, into the data assembler. A high

level on TxSYNC signals the start of a transmit symbol. Two

successive 6-bit words form a 12-bit symbol component. The

incoming data is assumed to be complex in that alternating

12-bit words are regarded as the in-phase (I) and quadrature

(Q) components of a symbol. Symbol components are assumed

to be in twos complement format. The rate at which the TxIQ

data is read will be referred to as the master clock rate (fMCLK).

The data assembler receives the multiplexed IQ data and creates

two parallel 12-bit paths with I and Q data pairs, which

compose a complex symbol. The rate at which the I and Q data-

word pairs appear at the output of the data assembler are

referred to as the IQ sample rate (fIQCLK). Because four 6-bit

reads are required at the TxIQ input to read a full 24-bit

complex symbol, fMCLK is 4 times the IQ sample rate (fMCLK = 4 ×

fIQCLK).

Once through the data assembler, the IQ data streams are fed

through two half-band filters (Half-Band Filters 1 and 2). The

combination of these two filters results in the sample rate

increasing by a factor of 4. Thus, at the output of Half-Band

Filter 2, the sample rate is 4 × fIQCLK. In addition to the sample

rate increase, the half-band filters provide the low-pass filtering

characteristic necessary to suppress the spectral images

produced by the upsampling process.

IF12 INPUT

Q INPUT

I INPUT

SDELTA1

XTAL

FSADJ

SDELTA0

OSCIN

ADC

CONTROL WORD 0

CONTROL WORD 1

Σ-Δ

M = 1, 2, ..., 31

OSCIN

MULTIPLIER

× M

÷8

÷2

÷N

REF12

REF8

÷2

MUX

DAC

DAC GAIN CONTROL

N = 3, 4

(fOSCIN)

(fSYSCLK)

(fOSCIN)

QUADRATURE

MODULATOR

DDS

SIN

HALF-BAND

FILTER 1

HALF-BAND

FILTER 2

CIC

FILTER

DATA

ASSEMBLER

COS

AD832x CTRL

BURST PROFILE CTRL

SERIAL INTERFACE

RxIQ

DATA

÷2

R = 2, 3, ..., 63

÷R

(fIQCLK)

(fMCLK)

AD9877

TxIQ

Rx IF

RxSYNC

RxIQ

REFCLK

MCLK

TxSYNC

Figure 15. Block Diagram

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