AD14060/AD14060L

Rev. B | Page 17 of 48

THREE-STATE TIMING—BUS MASTER, BUS SLAVE, HBR, SBTS

These specifications show how the memory interface is disabled (stops driving) or enabled (resumes driving) relative to CLKIN and the

SBTS pin. This timing is applicable to bus master transition cycles (BTC) and host transition cycles (HTC) as well as the SBTS pin.

Table 14. Specifications

5 V

3.3 V

Parameter

Min

Max

Min

Max

Unit

Timing Requirements:

SBTS Setup before CLKIN

12.5 + DT/2

12.5 + DT/2

ns

SBTS Hold before CLKIN

5.5 + DT/2

5.5 + DT/2

ns

Switching Characteristics:

Address/Select Enable after CLKIN

−1.5 − DT/8

−1.25 − DT/8

ns

Strobes Enable after CLKIN1

−1.5 − DT/8

−1.5 − DT/8

ns

HBG Enable after CLKIN

−1.5 − DT/8

−1.5 − DT/8

ns

Address/Select Disable after CLKIN

1 − DT/4

1.25 − DT/4

ns

Strobes Disable after CLKIN1

2.5 − DT/4

2.5 − DT/4

ns

HBG Disable after CLKIN

3 − DT/4

3 − DT/4

ns

Data Enable after CLKIN2

9 + 5 DT/16

9 + 5 DT/16

ns

Data Disable after CLKIN2

0 − DT/8

8 − DT/8

0 − DT/8

8 − DT/8

ns

ACK Enable after CLKIN2

7.5 + DT/4

7.5 + DT/4

ns

ACK Disable after CLKIN2

−1 − DT/8

+7 − DT/8

−1 − DT/8

+7 − DT/8

ns

ADRCLK Enable after CLKIN

−2 − DT/8

−2 − DT/8

ns

ADRCLK Disable after CLKIN

9 − DT/4

9 − DT/4

ns

Memory Interface Disable before HBG Low3

−1 + DT/8

−1 + DT/8

ns

Memory Interface Enable after HBG High3

18.5 + DT

18.5 + DT

ns

CLKIN

SBTS

ACK

MEMORY

INTERFACE

HBG

MEMORY INTERFACE

ADRCLK

DATA

MEMORY

INTERFACE

= ADDRESS, RD, WR, MSx, SW, HBG, PAGE, DMAGx. BMS (IN EPROM BOOT MODE)

Figure 14. Three-State Timing